A field emitter array generally comprises two closely spaced surfaces. The first, an emitter surface, has a plurality of pyramid-like projections which are generally perpendicular to the surface. The second, a gate surface, is a conductive layer substantially parallel to and insulated from the first surface. The gate surface normally has a plurality of apertures disposed above the tips of the emitter projections so that electrons emitted from these tips pass through the apertures when the gate surface is positively biased with respect to the emitter tips. The separation between the emitter tips and the gate surface is generally on the order of about one micron so that low potentials between the two surfaces induce large electron currents.
Field emitter arrays are used in many electron devices due to their inherent advantages over thermionic cathodes, including: (a) higher emission currents; (b) lower power requirements; (c) less expensive fabrication costs; and (d) ease of integration with other circuitry. Despite these advantages, the use of field emitter arrays in high frequency devices is limited by two requirements. First, obtaining the desired magnitude of emitter current and electron energy at the selected operating frequency requires that the geometry of both the emitter tip shape and the apertures be precisely defined. Second, the capacitance of the insulating layer must be low in order to produce a device with high input impedance at high frequency operation. Previously known field emitter array structures and manufacturing techniques have achieved only limited success in satisfying these two requirements.
For example, it is known how to fabricate field emitter arrays using silicon dioxide (SiO.sub.2) as the insulating layer, since it is easily fabricated using conventional deposition techniques or can be thermally grown on a substrate. U.S. Pat. Nos. 4,513,308 and 3,755,704 disclose examples of such fabrication techniques. The '308 patent discloses deposition of SiO.sub.2 to a thickness of about 1-4 microns, which results in a relatively high capacitance between the two surfaces. The '708 patent discloses a thin insulating layer having a thickness of about 0.5-2 microns. Because the insulating layer thickness is limited in order to ensure that small apertures are formed, the thinness of the insulating layer results in a high capacitance structure. In addition, such thin insulating layers are subject to pin-hole defects which can lead to early failure of the field emitter array. Thus, conventional SiO.sub.2 deposition techniques limit the frequency range of the field emitter array and can limit the mean time between failure.
U.S. Pat. No. 4,307,507 discloses a method for forming a plurality of sharp cathode tips by orientation-dependent-etching a plurality of holes in a substrate such as &lt;100&gt; oriented silicon, filling the holes with a suitable conducting material, and removing the "mold" substrate. This method allows formation of crystallo-graphically sharp emitter tips but, because conventional deposition techniques are used to deposit the insulator and gate metallization layers after the mold is removed, the final structure still has a relatively low impedance at frequencies above, for example, one megahertz (1 MHz).
Heretofore, field emitter array structures using semi-insulating GaAs as a thick uniform insulating layer have not been produced.